1. Field of the Invention
The present invention relates to a DC-DC converter and a control method thereof. Particularly, the present invention relates to a DC-DC converter which produces no backward current, which flows from a smoothing circuit to a synchronous rectifying circuit, when the load becomes light, and a control method thereof.
2. Description of the Related Art
In a DC-DC converter, a switching circuit is switched on and off in response to a pulse signal, to intermittently supply a DC voltage to an inductance element. In some cases, such a DC-DC converter adopts a synchronous rectifying method of supplying a returning current, which flows into the inductance element while no electricity is supplied thereto, to the load through the switching element.
FIG. 8 shows one example of circuit structure of an assumable DC (direct current)-DC (direct current) converter of a synchronous rectifying type. This DC-DC converter comprises a light load detecting circuit which switches off a synchronous rectifying switching element, in accordance with whether the load is large or small.
In the DC-DC converter shown in FIG. 8, a control circuit 10 detects the difference between an output voltage Vout from the DC-DC converter and a reference voltage E11, and sends a difference voltage Vd to a comparator 20. The comparator 20 compares the difference voltage Vd with a voltage V1, which corresponds to (for example, is proportional to) the current value of an inductance current (a current flowing from a switching circuit 40 to an inductor L51). The comparator 20 outputs a high level signal in a case where the voltage V1 is higher than the difference Vd, and outputs a low level signal in a case where the voltage V1 is lower than the difference voltage Vd.
A clock signal CLK having a constant frequency is input to a D-type flip flop circuit (hereinafter referred to as D-FF) 30 from a clock circuit 1. The D-FF 30 latches a power source voltage VDD supplied to its data input terminal (hereinafter referred to as D terminal) at a rising edge of the clock signal CLK, and outputs a high level signal from its output terminal (hereinafter referred to as Q terminal). The D-FF 30 is reset by a high level signal from the comparator 20. Thus, the D-FF 30 continues outputting a high level signal from its Q terminal from when the clock signal CLK rises until when the output from the comparator 20 becomes high level.
When the output from the Q terminal of the D-FF 30 becomes high level, a voltage of ON level (high level) is applied, through a level shift circuit 5, to an N-MOSFET (N-channel MOSFET; MOSFET:Metal Oxide Semiconductor Field Effect Transistor) 41, which is at the high side of the switching circuit 40. On the other hand, the logical AND of a voltage of OFF level (low level) having been inverted by an inverter 2 and an output signal from a light load detecting circuit 60 is applied, through an AND circuit 4, to the gate of an N-MOSFET 42 at the low side. Because of this, the N-MOSFET 41 at the high side is switched on, and the N-MOSFET 42 at the low side is switched off. Then, a current flows from a power source VCC into the inductor L51 and charges a smoothing capacitor C51.
When the output signal from the D-FF 30 becomes low level, a voltage of OFF level (low level) is applied to the gate of the N-MOSFET 41 at the high side of the switching circuit 40. On the other hand, a voltage of ON level (high level) inverted by the inverter 2 is applied through the AND circuit 4 to the N-MOSFET 42 at the low side. Therefore, the N-MOSFET 41 at the high side is switched off and the N-MOSFET 42 at the low side is switched on. Then, the current flowing in the inductor L51 flows through the N-MOSFET 42 at the low side.
When the pulse width (high level period) of a pulse output from the Q terminal of the D-FF 30 increases, the ON period of the N-MOSFET 41 at the high side becomes long. Further, the energy to be supplied from the power source VCC to the inductor L51 increases, and the output voltage Vout increases.
When the output voltage Vout increases, the difference voltage Vd obtained by the control circuit 10 decreases and the pulse width of the pulse signal output from the comparator 20 widens. When the pulse width of the pulse signal widens, the period during which the D-FF 30 is reset becomes longer and the pulse width of the pulses output from the Q terminal becomes narrower. Accordingly, the ON period of the N-MOSFET 41 becomes shorter and the energy to be supplied from the power source VCC to the inductor L51 decreases, thereby to reduce the output voltage Vout.
When the output voltage Vout is reduced, the difference voltage Vd obtained by the control circuit 10 increases and the pulse width of the pulse signal output from the comparator 20 becomes narrower. When the pulse width of the pulse signal becomes narrower, the period during which the D-FF 30 is reset becomes shorter and the pulse width of the pulse signal output from the Q terminal becomes wider. Accordingly, the ON period of the N-MOSFET 41 becomes longer. Further, the energy to be supplied from the power source VCC to the inductor L51 increases and the output voltage Vout also increases.
In this way, the output voltage Vout converges at a level at which the system is stable, thereby the output voltage Vout, which is table, is obtained.
In the DC-DC converter shown in FIG. 8, when the load is small, the current that flows in the inductor L51 is small. In order to detect this and stop the synchronous rectifying function, i.e., in order to switch off the N-MOSFET 42, the light load detecting circuit 60 is provided.
When the load is light, the load current decreases and the voltage V1 corresponding to the load current also decreases. Thus, the voltage signal V1 supplied to the positive input terminal (+) of a comparator 61, which constitutes the light load detecting circuit 60, decreases to become smaller than a reference voltage E61. Accordingly, the comparator 61 supplies a low level signal to the AND circuit 4, and the AND circuit 4 controls the N-MOSFET 42 at the low side to be kept off all time. Therefore, only the N-MOSFET 41 at the high side is switched on and off and no returning current flows backward from the inductor L51. Thus, it is possible to prevent a switching loss at the N-MOSFET 42 and save the power to be consumed.
In the DC-DC converter having the above-described structure, when the load changes from a heavy one to a light one, there is a risk that the N-MOSFET 41 at the high side is continuously kept off and the N-MOSFET 42 at the low side is continuously kept on. If this state continues, a backward current flows from the inductor L51 to the N-MOSFET 42. Therefore, the N-MOSFET 42 might be destroyed.
To explain it more specifically, when the load becomes small, the current, which has headed to the load, starts to flow into the smoothing capacitor C51. Therefore, the output voltage Vout increases and the difference voltage Vd output from the control circuit 10 decreases. Accordingly, the output from the comparator 20 is kept at high level continuously and the D-FF 30 continues to be reset. In this state, the Q terminal of the D-FF 30 continuously outputs a low level signal, skipping the outputting of pulse signals, which are to be output otherwise.
Therefore, the N-MOSFET 41 at the high side is kept switched off, and the N-MOSFET 42 at the low side is kept switched on.
Here, if the light load detecting circuit 60 detects the change of the load to a light one and the decrease of the load current I1 (if the comparator 61 outputs a low level signal), the AND circuit 4 outputs a low level signal and the N-MOSFET 42 at the low side is switched off. However, since the time constant of the light load detecting circuit 60 is large (generally, the time constant of the light load detecting circuit 60>>the time constant of the control circuit 10) in order to secure operation stability, the control to switch off the N-MOSFET 42 is delayed. Because of this, the state that the N-MOSFET 41 at the high side is off and the N-MOSFET 42 at the low side is on is maintained. In this state, after the forward current by the electromagnetic energy stored in the inductor L51 ceases to flow, the charges stored in the smoothing capacitor C51 flow backward to the N-MOSFET 42. In the worst case, this backward current destroys the N-MOSFET 42.
As a method of detecting an abnormal state of an output voltage from a power source circuit, a method of sensing a pulse waveform of the output voltage and detecting an abnormal state of the waveform is known. For example, the method is disclosed in Unexamined Japanese Patent Application KOKAI Publication No. 2005-210819.
This method detects the pulse width and pulse interval of the pulse waveform, which appears at the output terminal of the section prior to the smoothing circuit, i.e., the output terminal of the switching circuit, and detects an abnormal state of the power source. After this, the circuit according to this method outputs an abnormal state detection signal representing the detected abnormality.
However, even if an abnormal state of the output voltage from the DC-DC converter of FIG. 8 is detected by the abnormal state detecting method disclosed in the publication, the N-MOSFET 42 at the low side will be controlled after such an abnormal state of the output voltage occurs. Therefore, the abnormal state detecting method disclosed in the publication cannot prevent a backward current.